1. Field of the Invention
The present invention relates to semiconductor manufacturing and testing. The present invention further relates to probe cards that are used to perform test and/or burn-in procedures on semiconductor devices.
2. Related Art
Individual semiconductor (integrated circuit) devices (dies) are typically produced by creating several identical dies on a semiconductor wafer, using known techniques of photolithography, deposition, and the like. Generally, these processes are intended to create a plurality of fully-functional integrated circuit devices, prior to singulating (severing) the individual dies from the semiconductor wafer. In practice, however, certain physical defects in the wafer itself and certain defects in the processing of the wafer inevitably lead to some of the dies being “good” (fully-functional) and some of the dies being “bad” (partially functional or non-functional). It is generally desirable to be able to identify which of the plurality of dies on a wafer are good dies prior to their packaging, and preferably prior to their being singulated from the wafer.
To this end, a wafer test system may advantageously be employed to make a plurality of discrete pressure connections to a like plurality of discrete connection pads (bond or contact pads) on the dies. In this manner, the semiconductor dies can be tested and exercised, prior to singulating the dies from the wafer. A conventional component of a wafer test system is a “probe card assembly” (also called a “probe card”) which can include a number of components coupling electrical signals between tester processing circuitry and probe elements. Probe elements have tips which effect pressure connections to respective pads of the semiconductor dies during testing and burn-in.
FIG. 1 is a simplified diagram of a conventional test system 100. Test system 100 includes a chuck 110, wafer 120, devices under test (DUTs) 125, probe elements 130, probe card assembly 140 and tester 150. Chuck 110 supports wafer 120. Chuck 110 is coupled to a control mechanism (not shown) which positions DUTs 125 with respect to probe elements 130 during testing. Wafer 120 includes one or more DUTs 125. For example, DUTs 125 can be a number of semiconductor dies fabricated on wafer 120 which are undergoing testing in a manufacturing process.
Probe card assembly 140 is positioned between wafer 120 and tester 150. Probe card assembly 140 is responsible for coupling signals between probe elements 130 and tester 150. During testing, probe tips 135 on probe elements 130 contact each DUT 125 at pads 126 positioned at predetermined locations. Tester 150 then performs any number of conventional testing routines.
FIG. 2 shows an example probe card assembly 140 in further detail. Probe card assembly 140 includes a space transformer 210, interposer 220, and a printed circuit board (PCB) 230. Interconnection elements 215 couple space transformer 210 and interposer 220. Interconnection elements 225 couple interposer 220 and printed circuit board 230. Note only two interconnection elements 215 and two interconnection elements 225 are shown for clarity, however, many such interconnection elements 215, 225 can be used. Electrical signals at probe elements 130 are carried through space transformer 210 to interconnection elements 215, to interposer 220, to interconnection elements 225, and eventually to PCB 230. PCB 230 then interfaces with a tester 150 as shown in FIG. 1. Similarly, electrical signals including test commands and signal test patterns issued by tester 150 pass through PCB 230, interconnection elements 225, interposer 220, interconnection elements 215, space transformer 210, and eventually to probe elements 130.
As the number of DUTs 125 being tested in parallel increases and the number and pitch of contact pads 126 on each DUT 125 increases, the number of probe elements 130 and their density increases. Space transformer 210 serves as an interface between the relatively dense arrangement of probe elements 130 and the larger and less dense geometry of printed circuit board 230. In particular, space transformer 210 interconnects probe elements 130 and interconnection elements 215. Space transformer 210 primarily includes passive circuit elements such as wires or other electrical conduits for coupling signals from probe elements 130 to a larger spatial geometry of interconnection elements 215. Capacitors are also sometimes used in space transformer 210 to further condition electrical signals passing therethrough. Simple, low power electronic components such as relays are sometimes used to allow separate control of the powering on and off of the testing performed on individual DUTs 125.
Interposer 220 couples signals traveling between interconnection elements 215 and 225. Interposer 220 is optional and is used to further maintain alignment when the position of space transformer 210 is adjusted in a “z” direction perpendicular to the surface of a wafer (e.g., wafer 120). PCB 230 couples signals between interconnection elements 225 and tester 150. PCB 230 can include any type of electronic circuitry that supports testing. For example, PCB 230 often includes an interface unit to couple signals to and from a port on tester 150. PCB 230 can also include circuitry for converting signals sent in a test pattern by tester 150 for a particular number of expected devices under test to the actual number of devices under test in a given process. In this way, if tester 150 is configured to send a test pattern in 64 channels for 64 DUTs and only 32 DUTs are present in a particular process, PCB 230 can include processing circuitry to issue the test pattern on the appropriate 32 channels. Note probe card assembly 140 is illustrative. In general, different types of probe card assemblies exist with different components and configurations. For example, some probe card assemblies do not include an interposer and some probe card assemblies may not include a printed circuit board.
One design goal of probe card assembly 140 is to provide uniform output signals to tester 150. Several factors are increasing the demands made upon probe card assembly 140. First, input/output (I/O) speeds continue to increase. Accordingly, the clock rate at tester 150 continues to increase from a megahertz range to even a gigahertz range. Second, the number and density of probe elements 130 continues to increase with the increasing number of leads (also called pads) on DUTs 125. Further, pad and pitch sizes of DUTs 125 continue to decrease, thereby increasing the density of the contacting probe elements 130. These demands upon probe card assembly 140 make it more difficult to provide uniform output signals. Problems such as pin-to-pin skew, differences in rise time, and other parasitics can occur as electrical signals travel through probe card assembly 140 during testing. Such problems are exacerbated when electrical signals have to travel over an extensive path between probe elements 130 and tester 150.
One approach to handling the increasing demands upon probe card assembly 140 is to incorporate additional hardware in probe card assembly 140 to carry out testing functionality. For example, active electronic components can be mounted on printed circuit board 230. These active electronic components can carry out certain testing functionalities. In this way, the length of the electrical signal path is reduced since certain electrical signals only need to travel from the probe elements 130 to PCB 230 before being processed. This solution can be of somewhat limited benefit, however, since the electrical path between probe elements 130 and PCB 230 may still be too great to sufficiently reduce parasitics. Accordingly, it is desirable to position active electronic components which can support testing functionality even closer to probe elements 130. Moving active electronic components close to probe elements 130, however, results in design problems heretofore not faced in probe card assemblies. In particular, the dense packing arrangement of probe elements 130 would require that the active electronic components be packed densely as well. Among other things, this leads to a heating problem not encountered before in probe card assemblies.
Heating problems have been recognized with respect to wafers. Different test systems have provided cooling mechanisms for wafers. The cooling mechanisms are provided both to control temperature and to maintain even heating across a wafer. For example, in certain testing and burn-in applications a particular temperature condition must be maintained. See also, U.S. Pat. No. 5,198,752, issued to Miyata et al. and U.S. Pat. No. 6,140,616, issued to Andberg.